This invention relates generally to computer systems and more particularly to devices used to drive signals onto and receive signals from a computer bus.
As it is known in the art, computer systems generally include a device referred to as a central processor unit which is used to execute computer instructions to perform some function. The central processing unit generally referred to as a CPU communicates with other devices in the computer system via a communications network generally referred to as a computer bus or system bus. Other devices commonly coupled to the system bus include memory systems such as main memory and more persistent type of storage systems such as magnetic disk type storage systems. These devices, including the CPU, are generally not connected directly to the system bus but rather are coupled to the bus through a device called a bus interface.
The bus interface device for a CPU may be quite different than that for a main memory or for a magnetic disk device. Moreover, for persistent storage such as magnetic disk, an interface module called a I/O bus adapter is often used to interface the system bus to an I/O bus (input/output bus) to which are connected several disk storage devices. In general however, all of these interfaces on a particular bus use a common set of devices called bus drivers and bus receivers to send and receive logic signals with proper voltage levels and appropriate drive capacity to insure reliable transfers of data on the bus.
As it is also known, system buses generally carry information including address information, control information, and data. Buses transfer this information in a logical manner as determined by the design of the system. This logical manner is referred to as the bus protocol.
One problem that is common with system buses is that as the performance of a CPU increases that is, as the processing speed increases, it is necessary to provide a concomitant increase in bus transfer rate. That is, it is necessary to permit more address, control, and data to be transfered at faster rates on the bus so as not to obviate the advantages obtained by use of a faster CPU.
Buses can be so-called synchronous buses in which all transfers are synchronized to a common timing signal referred to as a clock signal or the buses can be asynchronous buses in which hand-shaking signals are used to transfer information as quickly as possible.
Several problems are associated with improving bus performance whether the bus is synchronous or asynchronous. A characteristic called cycle time gives an indication of the speed of a bus. For a synchronous bus, a cycle can be viewed as that period of time required to complete a transfer on the bus before a new transfer can begin. This minimum period determines the maximum clock rate.
In general, the minimum cycle time for a synchronous bus is related to noise in the clock generally referred to as clock skew, propagation delay from an asserting edge of the clock to the period of time that the data appears at the output of the device connected to the bus, and delay associated with driving the bus. The delay associated with driving the bus includes two components. The first one is the propagation delay through the bus driver and the second is the period of time necessary to have the bus settle.
Settling time is related to the amount of time necessary to have current on the bus from the last state of the bus settle out so that the driver for the next state of the bus can drive current on the bus in the appropiate direction. For example, for a "logic one" level, the driver connected to the bus typically sinks current from other devices connected to the bus, whereas for a "logic zero" the driver typicall sources current onto the bus to other devices connected to the bus.
Bus settling time is also related to the amount of time necessary to have reflections on the bus die out before data are received by receivers.
For an asynchronous bus similar electrical considerations are present to determine a minimum cycle time. For the asynchronous bus, the minimum cycle time for is related to noise in the handshaking signals , propagation delay from an asserting edge of the handshaking signals to the period of time that the data appears at the output of the device connected to the bus, and delay associated with driving the bus as indicated above.
Each of the above mentioned electrical parameters are further influenced by tolerances associated with the semiconductor fabrication processes used to provide the circuits interfacing to and feeding signals to the bus. For semiconductor processing certain characteristices such as resistances, capacitances, operating currents, voltages, and propagation delays, can vary greatly within a lot of devices and over different periods of manufacture of the devices. For lower speed buses this variation is often not a problem whereas, for higher speed buses, one solution has been to increase the bus cycle time to take into consideration expected processing variations as well as aging effects. The chief drawback with this approach is that it reduces the overall performance of the system and moreover, it may not be sufficient to handle all potential variations in characteristices provided by semiconductor processing.
As data rates on the system bus increases, it has become necessary to terminate the bus in an impedence which mininizes reflections on the bus. Common schemes for terminating a bus require a precise impedence determining circuit coupled at each of the two ends of each line of the bus. Termination of a bus in this manner presents a matched impedence line to signals on the bus. The matched impedance line has the effect of minimizing reflections on the bus since to the signal the line appears to be infinite in length. With reduced reflections caused by mismatched impedances, less time is required to wait until the signals on the bus settle before data becomes valid and thus speed at which data can be transfered increases.
One problem with this approach to terminating the bus is that by placing the termination at the end of the bus requires the selection of a high precision component but does not take easily into consideration variations between component impedances due to processing variations or changes over time. Further, termination of a bus at the ends of the bus still leaves portions of the bus between common bus conductors and individual devices on the bus unterminated. This can become a source of reflections on the bus as speeds on the bus increaes. These reflections are not adequately compensated for by the above mentioned approach.
Therefore, while use of a precise terminating impedance such as an externally coupled resistor generally provides a suitable impedance at lower operating frequencies of a bus, such an external termination still can require a system designer to allocate sufficient time for the bus to settle for buses operating at higher frequencies. Moreover, this technique is also suceptible to providing less than optimum performance at high frequencies due to variations in device characteristics caused by processing variations from device to device.
Further, such a technique does not easily allow for changing the termination resistance of a complicated bus. For example, a modification of a bus design may require a different resistance to terminate the bus. That is often bus termination resistance is determined on prototype devices. When actual devices are built however, the optiminal termination resistance may be different. To change the termination resistance requires a redesign of the bus interface devices and fabrication of a new lot of such devices. This is expensive and time consuming and hence undesirable.